1. Field of the Invention
The field of this invention relates in general to semiconductor processing. More particularly, the field of the invention relates to systems and methods of stripping photoresist and removing residues from a semiconductor substrate.
2. Background
Future semiconductor manufacturing technologies are expected to have stringent requirements for a variety of specific critical photoresist and residue removal processes, due in part to reductions in component size, increasing circuit speeds, and greater sensitivity of devices to surface contamination. These processes include, but are not limited to: 1) photoresist stripping following a high-dose ion-implantation (HDIS) process, 2) via cleaning, which means the removal of veils and residues following a via etch, particularly in the case where the dielectric layer through which the via is being formed is overlaying an aluminum or copper metallic layer, and 3) photoresist removal in the presence of a low-dielectric constant (low-k) material.
Current photoresist stripping methods are unable to cope with these new stringent requirements. For example, decreasing transistor sizes are making shallower and heavier doping levels necessary, which puts an additional burden on the photoresist mask used to protect the areas that will not be implanted. Another example has to do with vias, where residue free via surfaces are necessary for proper circuit function. Yet, such residues often contain metallic elements, and compounds of those elements with silicon and oxygen, and are therefore physically hard, chemically and reactive, and difficult to remove. As a final example, new requirements for increased speed of a semiconductor circuit dictate that the currently used quartz (silicon dioxide) or spin-on glass dielectric insulation between interconnects be replaced with materials having a lower dielectric constant. The reduction in the dielectric constant, k, reduces the capacitance from any one particular conductor line to an adjacent line, which simultaneously reduces crosstalk between these lines, improving signal speed and integrity. But photoresist removal can be difficult in the presence of a low-k dielectric material because conventionally used techniques are known to attack the dielectric material as well as the photoresist.
The use of a wet bath in the above-mentioned cases is becoming increasingly undesirable due to narrow feature widths, and the fact that materials are becoming increasingly sensitive to surface contamination and to damage from aggressive chemicals. Furthermore, there is increasing pressure to minimize the use of solvents or other wet chemical cleaning processes because of the associated environmental and health concerns, and the attendant costs. Therefore, photoresist stripping and residue removal processes which are critical to advanced circuit manufacturing will need to be accomplished by dry process techniques in the future.
Yet, in order for the integrated circuits fabricated by these dry processing systems to be cost competitive for the consumer electronics, communications and computation markets, the cost of these more difficult and expensive steps must be controlled. This means reducing processing time in the requisite equipment, which is expensive to own and operate. The dependence of wafer manufacturing costs on such processing times is typically multiplied by a factor of at least 10, since there will be that many more critical steps in manufacturing future integrated circuits. Many of the conventional photoresist removal processesxe2x80x94those not involving high dose ion implanted photoresist or low-k materialsxe2x80x94are typically easier to perform and efficiently completed in a variety of ashing systems.
Conventional dry photoresist removal systems and processes typically cannot simultaneously meet all the requirements of the aforementioned critical photoresist or residue removal steps, since they exhibit one or more of the following deficiencies: 1) removing photoresist too slowly to be commercially competitive, 2) popping of photoresist previously subjected to high dose ion implantation because of the necessity of high temperature removal (a wafer temperature greater than or equal to about 110 degrees Celsius) in order to achieve commercially acceptable rates, 3) being unable to remove difficult residues or photoresist layers without causing damage to, or sputtering of, exposed sensitive materials, and 4) causing the oxidative degradation or erosion of exposed low-k materials as photoresist is removed.
Typical current-generation photoresist removal systems use remote, low density plasmas generated with gas pressures on the order of 1 Torr as their source of (mostly neutral) reactive species. Typically they use oxygen as the principal process gas. In order to etch the photoresist in such systems the temperature of the wafer may be maintained at or above about 150 degrees Celsius. The problem at these temperatures is that oxygen atoms created in the plasma source can cause the rapid oxidation of photoresist, which is desirable, but at the cost of supplying the necessary activation energy primarily by thermal means. Addition of other gases such as fluorine, nitrogen and/or hydrogen can modestly accelerate the oxidation rate, by chemical means, but not enough to make the process at low wafer temperatures comparable to that at elevated temperatures. In fact, the addition of fluorine to accelerate the reaction can have negative consequences, since it may etch exposed areas of silicon dioxide.
Next, a more specific discussion of the relevant background will be given as it applies to exemplary semiconductor processing applications: 1) photoresist removal following a high-dose ion-implantation process, 2) via cleaning or residue treatment processes, and 3) photoresist removal in the presence of a low-k dielectric.
High dose ion implantation is increasingly necessary to create the very high doping levels needed in thin silicon layers which serve as the components of a transistor in advanced ULSI circuits. Unfortunately, high dose levels can cause crosslinking and degassing of the carbon-based polymers in the photoresist mask. This produces a much tougher and less permeable material, called crust, in the top 1,000 to 3,000 angstroms of the photoresist layer. Such photoresist is subject to xe2x80x9cpoppingxe2x80x9d under higher temperature conditions, producing large numbers of carbon-rich particles which may cause defects in the succeeding patterning steps for the integrated circuits. Avoidance of popping typically requires that the processing temperature be kept below some threshold value (about 110 degrees Celsius). Above this temperature the bulk photoresist under the crust evolves organic solvent, leading to a high pressure state within the bulk photoresist which pushes up on the crust above.
FIG. 1 is a schematic illustration of the potential problems that may be encountered hen stripping photoresist at the elevated temperatures necessary to achieve commercially feasible strip rates. Referring to FIG. 1, region 102 is an area of silicon wafer 101 which has been ion implanted. The ion implantation process has created a hardened crust 105 on the photoresist mask shown generally at 106. Crust 105 is a crosslinked version of bulk photoresist 104, the crosslinking being a result of the ion bombardment (in other words, bulk photoresist that is exposed to ion bombardment becomes crosslinked). Layer 103 is a sacrificial oxide layer generally having a thickness of about a hundred angstroms. Photoresist removal processes that occur at high temperatures can build up a high pressure 107 within bulk photoresist 104, due mainly to residual solvents in the bulk photoresist. The mask shown generally at 108 has xe2x80x9cpoppedxe2x80x9d from the elevated pressure, leading to carbon-containing particulate contamination 109.
Because of the high activation energy required for reactions between oxygen and the highly cross-linked polymer chains in the crust, etching by conventional oxygen-based ashing processes proceeds at a much lower and commercially unacceptable rate. This is especially true if the wafer is kept at temperatures less than about 100 degrees Celsius to avoid xe2x80x9cpoppingxe2x80x9d of the photoresist. Removal of bulk photoresist and photoresist crust must also be carried out without compromising the integrity of protective layers (usually silicon dioxide, such as oxide layer 103) covering the sensitive silicon areas that were just implanted. Thus, ion sputtering or etching of the protective oxide layer 103 must be kept as low as possible. Addition of fluorine to the feedgas increases the etch rate of the crust to a level sufficient to produce economically competitive rates of wafer processing, but causes some etching of the sacrificial silicon dioxide, or leaves residual fluorine in the chamber or on the substrate, which may be harmful in succeeding process steps. For these reasons, it may be undesirable to add fluorine to the feedgas composition.
In photoresist stripping systems based on microwave generated plasmas, gases added to the oxygen-based feedgas promote the more rapid etching of the crust but the rate is still not adequate for situations where ion doses had been at the high end of the implant range. Some of these systems now use RF biasing power applied to the wafer pedestal to increase the energy of ions (from the strip plasma) striking the wafer surface. Ion bombardment promotes rapid reactions of oxygen with the crust, but the current density of ions in such systems is typically rather low (i.e. less than about 0.3 mA/cm2), resulting in an undesirably high energy of ions at a given level of wafer biasing power. These ions could then cause sputtering of, or damage to, the silicon dioxide protective layer. As a result, there is a need for improved stripping of such hardened photoresist layers.
Via cleaning (removal of veils and treatment of residues) is a second example of semiconductor processing. Residues found lining via holes just after, for example, a dielectric etch, are often difficult to remove, whether by using acid, solvent, or plasma-based cleaning methods. Residues may contain a significant amount of the elements silicon and aluminum if the layer underlining the dielectric is aluminum and the etch process is continued to the extent that the aluminum is exposed. Conventionally, wafers are usually processed in an ashing chamber immediately following via etching, causing the aluminum-containing residues to be converted in part to compounds of aluminum and oxygen. Aluminum and oxygen containing compounds offer significant resistance to chemical and physical attack, since it will be appreciated that aluminum oxide is a hard, ceramic material. Furthermore, the smaller dimensions encountered in current technologies apply to vias as well, so vias are becoming increasingly narrow, and hence any residues contained inside are not as accessible.
The starting point for a typical via etching process is shown in FIG. 2A, and the resulting veils and residues in FIG. 2B. In FIG. 2A, photoresist 201 has been patterned on top of dielectric layer 202, where dielectric 202 may be, for example, silicon dioxide. The dielectric layer may have been deposited on top of a composite barrier layer, for example, TiN layer 203 and TiW layer 204. The barrier layers have, in turn, been coated on metal layer 205, which may be aluminum. Referring now to FIG. 2B, via 206 has been etched in dielectric layer 202. The etch may have been continued through the barrier layers such that metal layer 205 had been exposed, resulting in the deposition of etch byproducts in the form of veils 207, sidewall polymer 208, and residues 209. For the semiconductor device to function properly, the veils and sidewall polymer must be removed, and the residues either eliminated as well, or treated such that they can be more easily dislodged in subsequent steps (i.e., in a DI water rinse). The term xe2x80x9cresiduesxe2x80x9d will be used in this description to mean any kind of deposition of reaction byproduct, including veils and sidewall polymer.
Residues may contain a variety of etch byproducts, including, but not limited to, the following in both elemental and compound form: silicon, aluminum, carbon, fluorine, titanium, and oxygen. As a result, cleaning of these residues is becoming increasingly difficult in advanced circuit manufacturing, and frequently cannot be achieved with conventional dry residue removal systems. Typical current plasma-based downstream ashing chambers do not have the capability of inducing gas phase species to react chemically with residues to form compounds which are easily washed off in a deionized (DI) water rinse or mildly aggressive wet chemical bath. As a result, highly aggressive organic solvents are used extensively to remove residues. Aggressive organic solvents are expensive and involve potential hazardous waste disposal and safety issues; thus, there is a need for an improved plasma based method of removing residues that does not require aggressive organic solvents.
A third exemplary semiconductor processing involves the stripping of photoresist in the presence of a low-k material. As transistor sizes in ultra-large-scale integrated circuits shrink it is necessary to reduce the capacitance of the metal interconnection lines to each other to minimize the delays of signals and to reduce the xe2x80x9ccrosstalk.xe2x80x9d This permits circuits to maintain or increase speed as the size of the transistors is reduced, and can be accomplished best by using polymeric or other insulating materials on the integrated circuit chip which have a lower dielectric constant (k) than the conventionally used silicon dioxide. However, such low-k materials often have an organic or hydrogen content which is likely to be oxidized in the presence of the atomic oxygen typically used to strip photoresist. This is unfortunate, because oxygen atoms are the most effective species in current photoresist removal systems for the ashing of photoresist at economically competitive rates. As a result, typical photoresist removal systems are not able to rapidly and efficiently remove photoresist while avoiding degradation of low-k dielectrics.
Conventionally used silicon dioxide (SiO2) has a dielectric constant of about 3.9 to 4.0. Fluorinated oxides have a dielectric constant of about 3.5. Fluorinated oxides are sometimes described by the acronym FSG, or by the symbols SiOF and FxSiOy. There are a variety of other silicon-containing low-k materials that are not a fluorinated version of the conventionally used silicon dioxide. xe2x80x9cCarbon-doped glass,xe2x80x9d or SiOC, has a dielectric constant of about 2.5 to 3.1. The polysiloxanes HSQ, hydrogen silsesquioxane (HSiO3/2)n and MSSQ, methyl silsesquioxane CH3SiO1.5)n have dielectric constants in the range 2.3 to 3.0. These materials are sometimes referred to as spin-on dielectrics (SOD""s), or flowable oxides FOx (Dow Corning). Finally, there are low-k dielectric materials that do not contain silicon, and in fact are either purely organic or substantially organic. Fluorinated amorphous carbon (FLAC, or xcex1-CF) has a dielectric constant in the range 2.3 to 2.7. Polymeric materials include fluorinated poly(arylene ether) (FLARE, Allied Signal), fluorinated polyimides(DuPont), parylene, polyphenylquinoxaline (PPQ), benzocyclobutene (BCB), and the like. Members of this latter group of purely or substantially organic materials have dielectric constants in the range of about 2.0 to 3.0.
The problem with etching silicon-based low-k dielectrics in the presence of oxygen is that the material shrinks physically, and its porosity increases upon oxidation, resulting in an undesirable increase in dielectric constant. Ultraviolet radiation also can cause degradation of such materials by way of the breaking of silicon-carbon and/or silicon-hydrogen bonds in the material. Porosity is undesirable because it causes the film to be prone to absorb moisture from the air, which is released upon subsequent heat treatments. Moisture release causes so-called xe2x80x9cpoisoning,xe2x80x9d which is a contamination of metal interconnects as the metal is being deposited into the vias (holes) in the low-k material. In this situation the metal interconnect""s electrical resistance is greatly increased due to the chemical reaction of the water vapor with the metal being used to line or to fill in the holes.
Such low-k materials containing silicon can be even more sensitive to oxygen than the purely organic low-k materials. Oxidation of either HSQ or MSSQ converts Sixe2x80x94H bonds to Sixe2x80x94OH bonds, which cause the material to absorb moisture, become porous, and experience an increase in the dielectric constant. These events can lead to poisoning of the via. Materials such as Sixe2x80x94Oxe2x80x94C, and Sixe2x80x94Oxe2x80x94Cxe2x80x94H materials deposited by plasma CVD, can also undergo degradation by oxidation. Conventional processes have substituted hydrogen for oxygen, or provided in some manner a net reducing atmosphere in an attempt to relieve some of these problems, but the addition of hydrogen to an oxygen-based plasma decreases the photoresist etch rate to commercially unacceptable values and may not provide sufficient protection of the low-k material.
FIGS. 3A and 3B are exemplary of the types of problems encountered when stripping photoresist in the presence of a low-k dielectric. Referring to FIG. 3A, the pattern of photoresist layer 301 has been transferred to hard mask 302 (which could also be a chemical mechanical polish stop layer), and this pattern will in turn be transferred to low-k layer 303 to create via 304. Exemplary materials from which the hard mask may be fabricated include, but are not limited to, SiON, SiO2, and Si3N4. Photoresist layer 301 may be removed either prior to or during this via etching step. In either case, the use of oxygen-containing gases to strip the photoresist may cause an isotropic attack on horizontal surface 305, resulting in an undercut 306 of the hard mask.
FIG. 3B gives another example of the difficulties encountered when stripping photoresist in the presence of a low-k material, and illustrates one of several methods of performing a so-called Dual Damascene process. Referring to FIG. 3B, hard mask 312 (which may be, for example, silicon oxide or nitride) has been used to etch via 314 in low-k dielectric layer 313. Following this, photoresist 310 is used to etch a larger opening 317 in low-k layer 311, where the larger opening is axially aligned with via 314. The difficulty is that the low-k material is exposed on sidewalls 315 and 316, and this exposed area may be oxidized or degraded by chemical attack as the photoresist is removed. The sidewall may recede, causing the hole diameter to increase and undercutting the opening in the protective silicon oxide or nitride. This is undesirable since it makes the filling of the via with metal difficult, expensive and unreliable.
What is needed are systems and methods for stripping photoresist following an HDIS process, cleaning via veils and treating residues, and removing photoresist in the presence of a low-k material, at commercially viable rates, without photoresist xe2x80x9cpopping,xe2x80x9d excessive contamination, or degradation of the underlying materials.